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IDT74LVC112A 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS DUAL IDT74LVC112A NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET, 5 VOLT TOLERANT I/O
* 0.5 MICRON CMOS Technology * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * CMOS power levels (0.4 W typ. static) * Rail-to-Rail output swing for increased noise margin * All inputs, outputs, and I/Os are 5V tolerant * Supports hot insertion * Available in TSSOP package
FEATURES:
DRIVE FEATURES: APPLICATIONS:
* High Output Drivers: 24mA * Reduced system switching noise
This dual negative-edge-triggered J-K flip-flop is built using advanced dual metal CMOS technology. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements is transferred to the outputs on the negativegoing edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the holdtime interval, data at the J and K inputs can be changed without affecting the levels at the outputs. The LVC112A can perform as a toggle flip-flop by tying J and K high. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system. The LVC112A has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
DESCRIPTION:
* 5V and 3.3V mixed voltage systems * Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
Q PRE
Q CLR
K CLK
J
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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(c) 2004 Integrated Device Technology, Inc.
JANUARY 2004
DSC-4770/4
IDT74LVC112A 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Description Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND Max -0.5 to +6.5 -65 to +150 -50 to +50 -50 100 Unit V C mA mA mA TSTG IOUT IIK IOK ICC ISS
1CLK 1K 1J 1PRE 1Q 1Q 2Q
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VCC
1CLR 2CLR 2CLK 2K 2J 2PRE 2Q
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
GND
TSSOP TOP VIEW
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 4.5 5.5 6.5 Max. 6 8 8 Unit pF pF pF
NOTE: 1. As applicable to the device type.
PIN DESCRIPTION
Pin Names xCLK xCLR xPRE xJ, xK xQ, xQ CLK Inputs Clear Inputs (Active LOW) Preset Inputs (Active LOW) Data Inputs Data Outputs Description
FUNCTION TABLE(1)
Inputs xPRE L H L H H H H H xCLR H L L H H H H H xCLK X X X H xJ X X X L H L H X xK X X X L L H H X Q(3) xQ H L H (2) Q
(3)
Outputs xQ L H H (2) Q(4) L H Toggle Q(4)
H L
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = HIGH-to-LOW transition 2. The output levels in this configuration may not meet the minimum levels for VOH. Furthermore, this configuration is unstable; that is, it does not persist when either PRE or CLR returns to its inactive (HIGH) level. 3. Level of Q before the indicated steady-state input conditions were established. 4 Complement of Q or level of Q before the indicated steady-state input conditions were established.
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IDT74LVC112A 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL IOFF VIK VH ICCL ICCH ICCZ ICC High Impedance Output Current (3-State Output pins) Input/Output Power Off Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 0V, VIN or VO 5.5V VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V, VIN = GND or VCC -- -- -- -- -- -0.7 100 -- 50 -1.2 -- 10 A V mV A VCC = 3.6V VO = 0 to 5.5V -- -- 10 A Parameter Input HIGH Voltage Level Input LOW Voltage Level Input Leakage Current VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VI = 0 to 5.5V Test Conditions Min. 1.7 2 -- -- -- Typ.(1) -- -- -- -- -- Max. -- -- 0.7 0.8 5 A V Unit V
Quiescent Power Supply Current Variation
One input at VCC - 0.6V, other inputs at VCC or GND
--
--
500
A
NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2.2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
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IDT74LVC112A 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, VCC = 3.3V 0.3V, TA = 25C
Symbol CPD Parameter Power Dissipation Capacitance per Flip-Flop Test Conditions CL = 0pF, f = 10Mhz Typical 24 Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.7V Symbol fMAX tPLH tPHL tPLH tPHL tSU tSU tH tW tSK(o) Parameter Propagation Delay xCLR or PRE to xQ or xQ Propagation Delay xCLK to xQ or x Q Setup Time, Data before CLK Setup Time, PRE or CLR inactive Hold Time, data after CLK Pulse Width, CLK HIGH or LOW Output Skew(2) 2.3 1.1 0.7 3.3 -- -- -- -- -- -- 3.1 2.4 2.5 3.3 -- -- -- -- -- 500 ns ns ns ns ps -- 7.1 1 5.9 ns Min. 150 -- Max. -- 5.5 VCC = 3.3V 0.3V Min. 150 1 Max. -- 4.8 Unit MHz ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2 Skew between any two outputs of the same package and switching in the same direction.
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IDT74LVC112A 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 VCC(2)= 3.3V0.3V & 2.7V 6 2.7 1.5 300 300 50 Unit V V V mV mV pF
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
Propagation Delay
LVC QUAD Link
VCC 500 Pulse Generator
(1, 2)
VLOAD Open GND ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 VT tPHZ VT 0V tPLZ DISABLE VIH VT 0V VLOAD/2 VLZ VOL VOH VHZ 0V
LVC QUAD Link
VIN D.U.T. RT
VOUT
500 CL
LVC QUAD Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
DATA INPUT TIMING INPUT SYNCHRONOUS CONTROL ASYNCHRONOUS CONTROL
tSU
tH
tREM
INPUT
tPLH1
tPHL1
VIH VT 0V VOH VT VOL VOH VT VOL
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
LVC QUAD Link
Set-up, Hold, and Release Times
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE VT
LVC QUAD Link
OUTPUT 1
tSK (x)
tSK (x)
VT
OUTPUT 2 tPLH2 tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC QUAD Link
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
Pulse Width
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IDT74LVC112A 3.3V CMOS DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
XX IDT XX LVC XXXX Temp. Range Device Type Package
PG 112A 74
Thin Shrink Small Outline Package Dual Negative-Edge-Triggered J-K Flip-Flop with Clear and Preset -40C to +85C
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for Tech Support: logichelp@idt.com (408) 654-6459
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